Tech paper: Low impedance design in power circuits
In recent years, electronic circuits demand lower voltage yet higher current, reducing tolerance for voltage fluctuations. This shift arises from smaller semiconductor nodes and more complex IC functions. Achieving this balance necessitates significant impedance reduction.
The tech paper explores PDN design basics, decoupling capacitor types, arrangements, and key points for minimizing impedance via board design.
Table of contents
- Need for low-impedance design
- Relationship between power voltage variations (ΔV),
power current variations (ΔI), and power impedance (Z)
Background
- Methods to reduce power impedance
- Characteristics and structure of low-ESL capacitors
- Example of using 3-terminal capacitors
Solution
Impedance reduction—Cases
- Simulation overview
- Replacement with 3-terminal capacitors
- Notes on design
Impedance reduction—Effect verification
Conclusion
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